This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits (IC) may be formed from arrangements of one or more input/output devices, standard devices, memory devices, and/or the like. In one scenario, memory devices may include memory arrays arranged into memory cells and the associated circuitry to write data to the memory cells and read data from the memory cells.
In particular, the memory cells of a memory array, such as a random access memory (RAM) array, may be organized into rows and columns. The logic latches within these individual memory cells may be used to store a data bit that is representative of a logical “1” or “0.” These memory cells may also be interconnected by word-lines (WL) and pairs of complementary bit-lines (BL).
In a further scenario, one or more sense amplifiers may be connected to respective pairs of complementary bit-lines. A sense amplifier may be used to sense the low power signals swings on a pair of complementary bit-lines, where the power swings represent a data bit stored within an individual memory cell. The sense amplifier may then amplify the low power signal swings to a recognizable logic level, thereby allowing the data bit to be properly interpreted by logic outside of the RAM array.
In some instances, however, sense amplifiers may be affected by one or more process variations, which may lead to issues such as the creation of an offset voltage within the sense amplifier. In such instances, the offset voltage may result in an inaccurate determination of the value of the data bit stored within an individual memory cell.